AMD begins to add GDDR7 support to its Linux GPU drivers

AMD has started to add support for GDDR7 memory and several new graphics IP blocks to its open-source Linux kernel driver, which indicates that software enablement for the company's next-generation standalone GPUs is underway, reports Phoronix. While AMD does not identify the upcoming architecture, the changes are likely tied to its RDNA 5 project, but they don't necessarily herald an imminent launch.

AMD's existing Radeon RX 9000-series graphics processors based on the RDNA 4 architecture use GDDR6 memory, so the addition of GDDR7 identification to drivers is arguably the most explicit confirmation that AMD is setting the stage for its next-generation discrete Radeon graphics processors based on the RDNA 5 architecture.

AMD also submitted patches that enable IH 8.0, a new version of its Interrupt Handler IP block, as well as NBIF 7.10, the latest revision of the company's New Bus Interface. Several smaller patches make additional preparations for the new hardware. These changes follow earlier Linux driver work involving Display Core Next 6 (DCN6) as well as GFX 13.0.x, suggesting that AMD is gradually upstreaming support for multiple components of an upcoming GPU architecture. Yet, while enablement of IH8, NBIF 7.10, DCN6, and GFX 13.0.x clearly point to new graphics hardware, it does not necessarily point to new discrete GPUs, unlike the mention of GDDR7.

As revealed in August, 2025, Laks Pappu, Senior Fellow at AMD, is the lead architect for AMD's next generation datacenter GPU and discrete graphics platforms. Pappu was building next-generation "competitive 2.5D/3.5D Chiplet-based and monolithic Graphics SoCs on various packaging technologies," according to his LinkedIn profile before it was edited to remove those disclosures.

Essentially, Pappu's profile indicated that AMD's next-generation GPU architecture could support multiple physical implementations — including multi-chiplet and monolithic — depending on performance, cost, market requirements, and AMD's willingness to compete in certain market segments

AMD has already used a multi-chiplet design with its Navi 31 GPU, an implementation that kept graphics processing hardware on a large Graphics Compute Die (GCD), but disaggregated memory interfaces and caches into smaller Memory Cache Dies (MCDs). A more ambitious implementation could potentially distribute graphics processing resources between multiple dies, although Pappu's profile did not disclose how AMD intended to partition its future GPUs.

Such an approach would be considerably more complicated than separating memory and cache functionality. Multiple compute dies would require high-bandwidth, low-latency connections as well as mechanisms for synchronization and coherency, while software would ideally continue to see the set of chiplets as a single graphics processor.

Based on conventional GPU development cycles of roughly 2.5 to 3.5 years, RDNA 5 could already have been approaching tape-out or early post-tape-out stages when the information surfaced in August 2025, which means that the company is already likely to be testing the new GPUs internally.

Officially, AMD hasn't disclosed any details about its RDNA 5 architecture nor launch schedule, so take these developments with a grain of salt. For now, all we know for sure is that AMD is working on standalone RDNA 5-based GPUs, and they're likely to use GDDR7 in at least some configurations, assuming the AI-driven memory crunch doesn't choke supply of those chips even further for consumer applications.

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