Nuvacore reveals unconventional Core First CPU IP design strategy

When Nuvacore, a new CPU startup founded by legendary CPU and system architects Gerard Williams, John Bruno, and Ram Srinivasan, emerged from stealth earlier this year, it promised to "rewrite the rules of silicon," but did not say how it planned to do so. On Thursday, the company finally broke its silence and revealed that it is taking an unusual development approach that allows it to design a significant portion of its CPU core IP before committing to a particular instruction set architecture (ISA).

Traditionally, CPU developers start development of a new processor project with a particular ISA — such as Arm, RISC-V, or x86 — already selected. Although modern high-performance processors translate instructions into internal micro-operations and therefore separate the ISA from much of the underlying execution pipelines, the instruction set still influences numerous architectural decisions, including instruction decoding, register handling, memory ordering, and, of course, software compatibility.

Nuvacore says its Core First approach reverses at least part of this process. Instead of designing WarpCore around the requirements and limitations of a predetermined ISA, the company's engineers are developing a significant portion of the foundational CPU IP independent of a particular ISA. To a large degree, one can compare such an approach to the development of a car around its engine and not trying to fit an engine into an already developed platform.

"Rather than beginning with the constraints of an existing architecture and iterating from there, we are starting with the core itself," the company said in its statement.

As a result, the team may be able to better focus on the core's microarchitecture and optimize it for performance, power efficiency, and sustained workloads typical of modern data centers and AI infrastructure, the target application for the company. Nuvacore intends to select an instruction set later based on what works best for the systems that it and its partners plan to build.

There are obvious limits to how ISA-independent a CPU design can be. Eventually, WarpCore will need front-end logic designed around its chosen instruction set, and those architectural requirements will inevitably affect other parts of the processor. Nevertheless, substantial pieces of a modern CPU — such as execution units, branch-prediction units, data paths, caches, and portions of the memory subsystem — can be developed and evaluated before every ISA-related implementation decision is finalized.

In addition to not disclosing its ISA, which is arguably the biggest unanswered question surrounding the project, Nuvacore also has not disclosed the project's schedule, configuration, manufacturing process, power, or performance targets, though given the lack of the ISA commitment, one could say that the remaining details are not that important.

For now, the only thing that Nuvacore discloses about WarpCore is that it is "a new class of general-purpose CPU designed specifically for the sustained performance and power-efficiency requirements of AI infrastructure and contemporary data centers."

AMD's ambidextrous strategy returns?

Nuvacore's approach is not entirely without precedent. Under CEOs Rory Read and Lisa Su, AMD spent part of the 2010s pursuing an "ambidextrous" strategy intended to let it address x86 and Arm customers by sharing substantial processor and platform IP.

Arguably the most detailed part of the initiative was AMD's SkyBridge platform, announced in 2014. Under SkyBridge, AMD envisioned pin-compatible 64-bit Arm and x86 systems-on-chips that were to use AMD's own Puma+ x86 cores and Arm's Cortex-A57 cores with common platform infrastructure. Separately, AMD developed its custom 64-bit Arm K12 core under Jim Keller that was supposed to share microarchitecture features with Zen. Ultimately, due to lack of resources, SkyBridge was ultimately scrapped, while K12 never became a commercial product as AMD only pursued x86 Zen cores. The difference is, of course, that Nuvacore appears to be taking the idea further by deliberately postponing the ISA decision for WarpCore.

Since Nuvacore is still just a startup, we can only wonder whether its business plan includes marketing of CPUs at all. Nuvia, which was also founded by Williams and Bruno along with Manu Gulati, was acquired by Qualcomm and ultimately shaped the company's Snapdragon X Elite SoCs. In that light, its approach could give the company considerable commercial flexibility.

By developing much of its WarpCore design without tying it to a particular ISA, the company could potentially adapt the technology to the requirements of a future customer or partner. An Arm licensee could use the underlying core technology for an Arm implementation; another customer could choose RISC-V or another ISA. An established x86 vendor could potentially acquire or license the underlying microarchitecture and create its own x86 CPUs if it needs to.

Nuvacore, of course, has not indicated that such a transaction is its objective, but keeping WarpCore ISA-agnostic for as long as possible potentially broadens the number of companies to which its CPU technology could be valuable.

All in all, the Core First announcement tells us considerably more about how Nuvacore intends to develop WarpCore than what the processor itself will eventually look like. But if the company really does keep its ISA options open until relatively late in development, WarpCore represents an unusual attempt to separate development of a high-performance CPU microarchitecture from one of the decisions that normally defines a processor project from its earliest stages.

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