Hot Chips 2026: Arm details AGI server CPU with two 70-core N3P chiplets — touts 2 TB/s UCIe fabric link and 12-channel memory controller

This Tom's Hardware Premium article is free to read with a Tom's Hardware account; no payment necessary. We're offering free access from August 23 to 26 so you can read all of our reporting from Hot Chips.

When Arm introduced its AGI data center CPU, which it will ship starting in late 2026, the company revealed key specifications but omitted many technical details. It said nothing about the processor's performance at the time. This week at Hot Chips 2026, Arm filled many gaps about the architecture and design decisions of its AGI CPU, disclosed that the processor works as planned, published planned configurations, and said it is on track for commercial shipments in the coming months.

Many cores

Arm's AGI is a dual-chiplet data center processor that packs 64, 128, or 136 Neoverse V3 cores (10-wide frontend and decode, 10-wide dispatch, 8-wide retire, 384+ entry OoO window) running at 2.80 GHz – 3.70 GHz. The processor is equipped with two 128-bit vector engines and 2MB of L2 cache per core, as well as up to 272 MB of system-level cache. Each CSS V3 chiplet consists of 50 billion transistors, contains 70 V3 cores, a six-channel memory subsystem supporting up to 3 TB of DDR5-8800 memory (6 TB per socket), and connects to its sibling using a 16 ×16 UCIe macros running at 32 GT/s with an aggregated bandwidth of 2 TB/s. On the I/O side of things, Arm's AGI has 96 PCIe 6.0 lanes utilizing the CXL 3.0 protocol on top for memory expansion, four PCIe 4.0 lanes, and I3C, I2C, and SPI interfaces. The CPU has a thermal design power of 300W.

At a high level, Arm's AGI does not look too different from CPUs from AMD, Intel, and Nvidia: it has many cores, plenty of cache, a high-performance memory subsystem, and dozens of PCIe lanes with CXL. However, several design choices from Arm buck some usual trends from other CPU makers.

Unorthodox design choices

The first thing that catches the eye is that Arm chose two largely self-contained SoC chiplets made on TSMC's N3P technology, which places both compute and I/O on the same die, and decided not to go with the usual heterogeneous multi-chiplet designs used by AMD, Intel, and now Nvidia, all of whom separate compute and I/O chiplets.

While AMD, Intel, and Nvidia use their heterogeneous multi-chiplet approach to pack more compute capability and deliver more performance, it looks like Arm's decision is fundamental to its combination of enormous memory bandwidth (844.8 GB/s when used with DDR5-8800, though such memory still has to make it to the market) and <100-ns DRAM latency. As AGI's memory traffic does not have to travel to another chiplet with a memory controller, it can reduce latency and potentially achieve higher performance in latency-sensitive workloads, including some single-threaded and agentic AI workloads.

Each chiplet uses an 8 × 9 CMN-S3 mesh (a low-latency interconnect) to connect CPU cores, memory, I/O, and accelerators. It incorporates a 128 MB distributed system-level cache, snoop filtering, and hierarchical caching through HN-S, or Super Home Node, a piece of logic that acts as a distribution center for handling traffic and data through the chip to speed up communication.

The important point is that CMN-S3 is not just an internal CPU mesh, as Arm designed the coherent system to extend outside of the die to extend coherency beyond the die and the socket. The approach is conceptually closer to Intel's distributed Xeon 2D mesh (though Xeon is moving on to a 3D mesh with Diamond Rapids) than AMD's EPYC architecture, where compute chiplets connect to a central I/O die that hosts the memory controllers and Infinity Fabric infrastructure. This essentially proves that Arm appears to have optimized AGI's chiplets for memory locality, bandwidth, and latency, but not exactly for compute performance density, modularity, yield, and ease of manufacturing like AMD.

Arm revealed at Hot Chips that each chiplet physically contains 70 Neoverse V3 cores, but the complete product exposes up to 136 cores, which means that four cores are redundant and are incorporated to increase yield.

Capable memory subsystem

Arm positions its AGI CPU primarily for AI servers and agentic AI systems, in particular. Since memory performance plays a big role in many agentic AI workloads, Arm implemented a capable coherent NUMA memory subsystem. The NUMA subsystem features two six-channel DDR5 subsystems located in each chiplet, which can potentially provide a total of up to 845 GB/s of bandwidth. If a core needs memory attached to the other chiplet, the request can cross the coherent die-to-die connection, though at a cost of latency. Arm's goal is to provide as much bandwidth per core as possible, which is why AGI supports everything up to DDR5-8800.

The DDR5 controllers within Arm's AGI CPU are quite sophisticated too. They support numerous features to maximize performance in real-world workloads, including fully out-of-order command scheduling, bank-parallelism-optimized address mapping, and programmable page policies to improve DRAM utilization and extract more effective bandwidth from the memory subsystem, while anti-starvation mechanisms help maintain predictable service under heavy load.

In addition, Arm also implements memory-bandwidth limiting and monitoring through Memory Partitioning and Monitoring (MPAM) along with QoS-based traffic prioritization and congestion feedback to manage contention when multiple cores and I/O devices compete for DRAM bandwidth. The memory subsystem also features extensive RAS capabilities, including single-DRAM-device failure correction with Chipkill-class protection, memory scrubbing, row-hammer mitigation, repair support, error injection, and RAS error logging.

Capable memory subsystem

Now that Arm has shared so many details about its AGI CPU, the lingering question is the performance of the processor itself. Arm still has not published conventional benchmark results such as SPEC CPU2017, SPECrate, integer/floating-point throughput, or direct socket-to-socket comparisons against current AMD EPYC or Intel Xeon processors in real-world server workloads.

The main performance claim that Arm has made is '2X performance per rack versus the latest x86 platforms' based on estimates, which is not even remotely a detailed performance claim. Perhaps, following Nvidia's lead, Arm prefers to compare the per-rack performance of its CPUs, as they are made to work in racks. However, this is clearly an unconventional way to evaluate processors.

Image 1 of 21

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)

(Image credit: Arm)